Stratix III MLABs are slow

What speed grade? Is it the read or write side? I've had problems on the write side in that the write in the memory is negative edge, so your requirement is really 300MHz. The write registers need to be placed very close to the MLAB for this. The fitter should be able to do this, but I've seen issues. Another issue is if you're combining MLABs, i.e. if the write addresses fan-out to several MLABs, that can be very tight to do.

You could probably do an auto-sized floating LLR on each of these, although I'm not sure how good the results will be. You could try forcing some of these MLABs into M9Ks if they're available. Another thought is to make the write-address negative edge(if writing is your problem). This moves the 300MHz requirement from being wraddress_regs->MLAB back a stage to previous_regs->wraddress_regs. I'm not sure if this will work though, as it may always infer a half-clock cycle from the wraddress to the MLAB, but just an idea.

If it's always cases where a single wraddress reg fans out to multiple MLABs, you could replicate that one(the forum should have other stuff on register duplication). Just some thoughts.