Stratix III LVCMOS

To which document are you refering? Previous Stratix III device handbooks specified maximal input and output toggle rates for various IO standards in the datasheet section. Depending e.g. on currents strength values between 250 up to 550 MHz had been given for LVCMOS.

Now, the toogle rate tables have been removed. Without refering to the removal of datasheet specifications, the knowledge base says:

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From Stratix III, Stratix IV and Arria II GX devices onwards, Altera uses system-level specifications such as external memory interface specifications as an indication of I/O buffer performance. Actual achievable I/O signaling frequencies depends on design and system specific factors and is best determined using HSPICE / IBIS simulations. Altera will discontinue publishing the I/O toggle rate specifications in the device data sheets.

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For the recent V2.1 device manual, this general remark has been added under device performance:

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General-purpose I/O standards such as 3.3, 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2 LVCMOS at 100MHz interfacing frequency with 10pF load.

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Obviously, there is a change in the way, IO speed numbers are presented to the user. In my view, the datasheet is focussing more on realistic IO speed caculations for the interface as a whole, including e.g. typical load input capacitances. By only presenting slogan-like toggle rates, this point has been apparently often ignored.

Personally I would expect no problems when operating the DAC at 200 MHz data rate. The most critical signal is the 200 MHz clock, it would be better to use a differential I/O standard for it. The data lines are operating at only half the toggle rate. But you should care to adjust the driver impedance to the PCB traces.

I don't think that Stratix III single ended IOs are slower than of Stratix II.

Thanks. I was hoping there was not a strict limitation on the toggle rate.

I was not able to post the link to the document (forum rules if you have less than 5 posts). Here is the link without the www prefix:

altera.com/products/devices/stratix-fpgas/about/io-connect/stx-io-connect.html

I don't think that the numbers in this documented provide a resonable comparison between Stratix II and III IO behaviour. It also seems to contradict the above quoted politics not to specify "actual achievable I/O signaling frequencies".

As an actual difference between both FPGA families, due to Stratix III has less drive strength, although the core speed is obviously higher. Less drive strength means lower speed when driving heavy capacitive load. However, Stratix III is still able to drive 25 and50 ohm at 3.3V node with matched source sided termination. It's hard to imagine that it would be limited to 167 MHz with a moderate load.