Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorStratix III LVCMOS
Greetings, Altera's comparison chart of I/O standards for the Stratix family shows the maximum speed for LVCMOS is 300 MHz for Stratix II, but only 167 MHz for Stratix III. I have a DAC ...
Altera_ForumHonored Contributor
Honored ContributorI don't think that the numbers in this documented provide a resonable comparison between Stratix II and III IO behaviour. It also seems to contradict the above quoted politics not to specify "actual achievable I/O signaling frequencies".
As an actual difference between both FPGA families, due to Stratix III has less drive strength, although the core speed is obviously higher. Less drive strength means lower speed when driving heavy capacitive load. However, Stratix III is still able to drive 25 and50 ohm at 3.3V node with matched source sided termination. It's hard to imagine that it would be limited to 167 MHz with a moderate load.
