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Altera_Forum
Honored Contributor
Honored ContributorStratix III DE3 and DDR2
Hello, I am using the Terasic DE3 development board to create a Qsys SoC with a NIOS2, DDR2 memory (for an 1 GB RAM SODIMM module). I am following Terasic's pinout for all the DDR2 pins, but ti...
LaiMickey
New Contributor
New ContributorMe too.
But I think we can ignore this Critical Warning.
The pin locations of mem_clk[0] and mem_clk[1] are the DDR2 SO-DIMM socket pins.
They solder to the FPGA pin. Thus, we can not change the pin locations of mem_clk[0] and mem_clk[1].
The problem is somewhere else. 😕
LaiMickey
