Altera_Forum
Honored Contributor
Honored ContributorStratix III DE3 and DDR2
Hello,
I am using the Terasic DE3 development board to create a Qsys SoC with a NIOS2, DDR2 memory (for an 1 GB RAM SODIMM module). I am following Terasic's pinout for all the DDR2 pins, but timing isn't being met for Read and Write as Altera complains about the following: Critical Warning: Warning (307018): Memory clock pin mem_clk[0], mem_clk[1] must be placed on the same edge of the device Critical Warning: Warning (307020): mem_clk[0] was placed on the right edge of the device Critical Warning: Warning (307020): mem_clk[1] was placed on the bottom edge of the device Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions I also notice when I try to read and write to my memory, on occasions it gives garbage and I suspect its this timing that is not correct. Anybody have any experience with this or any clues on what I could try? Salman
