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Altera_Forum
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16 years ago

Stratix III CLK Input Not Driving FPGA

I'm having a clock related issue with a Stratix III (EP3SL70F484) part on a custom PCB. The board is setup to feed a 1.8V 12MHz clock signal to the CLK0p pin on the FPGA. The clock signal originates ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

The I/O Standard is configured as 1.8V. But you got me thinking, so I checked the corresponding VCCIO lines and discovered that the 1.8V supply was not putting out 1.8V! (the power supply upstream is not normally enabled, and when it is enabled, does not supply enough voltage for the 1.8V digital supply). After fixing the issue with the power supply upstream, the power supply produces 1.8V and VCCIO now receives the proper voltage. Like magic, now the FPGA sees the clock, and my test program strobes the LEDs.

In an ideal design, all the circuitry for a given I/O bank would use the same supply as the VCCIO pins -- stepping down from a different voltage source added a whole other layer of complexity, especially when one supply is disabled, and the other is not. Oh well -- live and learn, I suppose.

Thanks jakobjones for all your help!