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Altera_Forum
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16 years ago

Stratix III CLK Input Not Driving FPGA

I'm having a clock related issue with a Stratix III (EP3SL70F484) part on a custom PCB. The board is setup to feed a 1.8V 12MHz clock signal to the CLK0p pin on the FPGA. The clock signal originates ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Yes, I probed the clock and it looks OK (12MHz, 1.7V Pk-Pk) although the signal is a bit overdamped (12ns rise/fall time, out of 83ns period) I wouldn't expect it not to work. The clock is generated by a 3.3V crystal controlled clock oscillator that is only connected to the FPGA through a resistor divider, as I mentioned before.