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Honored Contributor

16 years ago

Stratix III CLK Input Not Driving FPGA

I'm having a clock related issue with a Stratix III (EP3SL70F484) part on a custom PCB. The board is setup to feed a 1.8V 12MHz clock signal to the CLK0p pin on the FPGA. The clock signal originates ...

Altera_Forum

Honored Contributor

16 years ago

Well the signaltap served it's purpose. It told us two things:

1 - The FPGA is getting programmed.

2 - You have no clock.

Have you probed the via at the FPGA for the clock?

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Stratix III CLK Input Not Driving FPGA

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