Stratix III CLK Input Not Driving FPGA

Thanks for the reply!

I'm pretty sure the FPGA was getting configured, since the current draw would change markedly after programming. The LEDs connected to I/O lines were weakly pulled high before loading the SOF, but not afterwards.

I tried adding a signaltap instance to the dummy VHDL, but when I tried to acquire data, it would sit waiting for the clock. It would seem that internally, the clock signal is not getting through. But that does not explain why the LEDs would sometimes strobe in the past. I have not observed the LEDs to strobe after adding the signaltap interface, however.

Interestingly, after adding the signaltap interface, the current for the board after loading the SOF is always 400mA (previously it was 400mA when the LEDs strobed correctly, and ~1A when the LEDs did not strobe at all). Perhaps there is an optimization quirk/error in the fitter that was causing the exceptionally high current?

It feels like the problem changes as I try to debug it -- I'm completely stumped on this one.