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Altera_Forum
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16 years ago

Stratix III CLK Input Not Driving FPGA

I'm having a clock related issue with a Stratix III (EP3SL70F484) part on a custom PCB. The board is setup to feed a 1.8V 12MHz clock signal to the CLK0p pin on the FPGA. The clock signal originates ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Are you sure the FPGA is getting configured? The board will likely draw more current with the FPGA not configured.

I would add a small signaltap instance to your design. If you can connect to the signaltap instance, you know your design is running and you can see if the clock is running or not.

Jake