Stratix III alt_lvds Timing Requirements not met in speedgrade C2

Hi,

Can you try to do this:

Open TimeQuest Timing Analyzer in Tool Menu.

In Contrainsts Menu, choose Generate SDC file from QSF

Add into *.SDC file these lines:

set_time_format -unit ns -decimal_places 3

create_clock -period 20 -name clk [get_ports {clk}]

set_clock_groups -exclusive -group clk

(clk is name of clock signal used in your design)

Open Setting project and add this *.sdc file into TimeQuest Timing Analyzer

Hope it works.