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Altera_Forum's avatar
Altera_Forum
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18 years ago

Stratix IIGX question of comprehension

Hey all, I'm working with a PCIe development board that's equipped with (among other things) a Stratix II GX FPGA and 2 SFP channels that I've outfitted with cages from D-Link to convert the SFP p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Suggestion. Try simulating just the receiver in a basic design with the output of the receiver brought out to pins. This will tell you the data bit order for the received data. You could also use SignalTap II to analyze the internal nodes of the receiver in your design real time on the board. Like a logic analyzer that is able to probe the internal nodes.