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Altera_Forum
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17 years ago

Stratix II GX transceivers and REFCLK input clock

Hi, In a design involving a Stratix II GX 30 we are looking at the possibility to input one reference clock to the transceivers. Therefore, the reference clock input pin of one quad will need t...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Your latter question is a good one? And I don't believe Altera releases jitter characterization for the various clock routing paths.

Therefore, I can only speak from experience. I do have a single using 16 transceiver channels. I have 4 reference clocks (each as an input to 4 seperate quads) and those 4 reference clocks are made available to all other quads (see the attached PDF). The output data rate on each transceiver is about ~3Gbps max.

I do not see noticeable differences in jitter performance between the transceiver outputs. However, what we did observe is that the various reference clocks to interfere with each other.

So if I shut down reference clocks 2 and 3, the overall transmitter output jitter improves. Basically the more reference clocks I enable the more the jitter increases. (And we've shown it's not on the board but in the FPGA). However, in my case, I believe it is primarily due to the relationship in frequencies of the reference clocks.

Jake