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Altera_Forum
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17 years ago

Stratix II GX transceivers and REFCLK input clock

Hi, In a design involving a Stratix II GX 30 we are looking at the possibility to input one reference clock to the transceivers. Therefore, the reference clock input pin of one quad will need t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

Thank you for the information.

To ensure the design is working and that the right routing resources are used then a post routing simulation or a board would be the way to ensure it works to go further than compile process not flagging an error. Is it not possible to see the kind of routing used with the chip editor ? I have tried to use the chip editor but was not very successful at seeing the routing resources used. Moreover, is there any behavior difference to expect between the clock directly availbale to a transceiver and one provided via the interquad bus (jitter performance mainly) ?

Best regards,

JF

Best regards,

JF Hasson