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Altera_Forum
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16 years ago

Stratix II GX Transceiver - Pattern recognition in rx-data

Hi,

I have a transceiver-design with an optical loopback-wire. the datastream is a 32b binary counter with a clock of 120 MHz. My alt2gxb is configurated as followed:

- basic mode, double data width (32b), rate 3840 Mbps

- 8b/10b-coding

I see the received data at the 8 LEDs of my development-board only after some resets. Then it works stable for hours. Once I reset the design again, there are crazy patterns to see.

I assume the reason is an incorrect handling of either BYTE ORDERING BLOCK or PATTERN ALIGNMENT. Is it really necessary for the designer to have a constant pattern or control data in the 32b-datastream? That would decrease the capacity of the line...

What can I do to get a stable design in this case?

thank you

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You have to have some way to perform word alignment. This is typically done by transmitting a known word pattern that the receiver can look for. Then it can slip bits until aligned. You at least need to perform this alignment on startup. Typical applications using 8B/10B will constantly transmit the comma character K.28.5 when not transmitting valid data.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi! First: Thanx for your quick reply, jake!

    After getting the modelsim simulation library to work, I could see that there probably is a different problem with the TX phase compensation fifo. In modelsim, I see that in tx_digitalreset-mode the K28.5 word is transmitted. After reset time, the data word at the tx-input is arbitrary and constant "FF0F33FB". I looked up the 8b/10b-coding table of the handbook to see what my serialized signal should be. Instead seeing it, I get some undefined states in the signal; mixtured with the 8b/10b-coding. While searching for the reason, I found that some tx-internal values have undefined bits, too:

    sim:/testbench/u_0/u_7/nlilo/ser_datain:

    U00U1101010010111010

    sim:/testbench/u_0/u_7/nlilo/wire_dprioout: UUUUU... later some 0 and 1 but always U inbetween.

    sim:/testbench/u_0/u_7/nlilo/td_in_txd and also

    pi_in_txd_ch, pi_in_txd_ch_dprio, pi_out_txd:

    00U0000000000U0000000000U0000001000U10101111

    Also, the debug_tx_phase_comp_fifo_error signal is U all the time.

    Daniel