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Altera_Forum
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18 years ago

Stratix Ii Gx And Alt2gxb Ip

Hello, I'am new on FPGA and I have some questions. I try to implement the alt2gxb ip on a stratix II gx. here all is ok. In my design I receive datas from an optical fiber with t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

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Hello,

I first understood, that you have single ended signal input signal, which would be unlikely for gigagbit datarate. In your HDL design, you need only an single input port per GXB channel that is connected connected to GXB rx_datain. As you assign a differential IO standard to this input in pin planner or assignment editor, you get two phsysical pins for one logical signal.

Regards,

Frank

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thanks for your response I understand better now.

But in my VHDL top level I've got two signals (from optical fiber) and only one rx_datain.

I'am a few disappointed because I must assign only one rx_data signal.

Have you got a solution to my probleme.

In my VHDL I use several entity and I must make the interconection in the top level. The GXB is not the top level of my design.

If you want I can post my top level ?

thanks a lot for your help