Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorStratix Ii Gx And Alt2gxb Ip
Hello, I'am new on FPGA and I have some questions. I try to implement the alt2gxb ip on a stratix II gx. here all is ok. In my design I receive datas from an optical fiber with t...
Altera_ForumHonored Contributor
Honored ContributorHello,
I first understood, that you have single ended signal input signal, which would be unlikely for gigagbit datarate. In your HDL design, you need only an single input port per GXB channel that is connected connected to GXB rx_datain. As you assign a differential IO standard to this input in pin planner or assignment editor, you get two phsysical pins for one logical signal. Regards, Frank
