New Contributor
Regular ContributorHi,
Could you check the nStatus to see if it is high to indicate that the FPGA is ready? May I know what is the issue that you are facing on the JTAG? Do you have another board to test it out?
New ContributorHello,
Thanks for your quick response. Now we are testing the single FPGA chip for our customer, we use jumper wire to connect all the required pins through socket, then power up all power pins (VCCINT, VCCIO, VCCPD) by a power supply instrument and connect all JTAG pins (TCK, TMS, TDI, TDO) to the XJTAG. In the JTAG software, we could not get any return data from TDO. I checked nSTATUS, it was low. Is that means the FPGA is not ready? So how can we let it ready? are there any additional setup?
Best,
