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Honored ContributorStratix II clock signal generation
Hi All.
I have just started on FPGA's , and am still getting to grips with VHDL. I have a task in which involves the usage of a Stratix II FPGA to generate a variety of clock signals. Would someone be able to give me some information on how to do this. It would be greatly apprecated, Aoedogg.1 Reply
Altera_ForumI suggest you start with the Alter PLL user guide
http://www.altera.com/literature/ug/ug_altpll.pdf
