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Altera_Forum's avatar
Altera_Forum
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13 years ago

Stratix Hardware design

hi guys,

i am using Stratix V device for our new design, i have a problem when doing the power estimated, we want used two type of GX lane, one is 2.5G SerDes and the other is PCIE GEN3 hard IP. we i used the EPE for power estimation, the table show different VCCA(2.5V and 3.0V) and VCCL(0.85V and 1.0V) voltage, should i used different voltage input for each GXB bank. i am doubt about this, hope someone can solve my problem, thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I would say the most reliable way to check is to instantiate the transceiver blocks with the necessary settings in Quartus and run the Fitter. The pinout file will give you the voltages for each power pin or tell you if there's a conflict. You can also experiment with the I/O Assignment Analysis under the Processing menu though I haven't experimented with that as much. Honestly, if you're setting up the hardware, it's probably not a bad idea to add as much detail in the pin assignments as possible to make sure there are no conflicts before making your board. In my design, I added memory controllers, etc. to make sure everything played nice before I got too far into my schematic.

    The pin connections guidelines are also another very good resource: http://www.altera.com/literature/dp/stratix-v/pcg-01011.pdf