Altera_Forum
Honored Contributor
14 years agoStratix-3 to Pic18F4550
Hi all,
I'd like some suggestions to a potential design I'm writing up. I have a the stratix-3 dsp devel kit, it contains the stratix-3 devel board plus an ADC/DAC board connected via one of the hsmc connectors. I take some data on the adc and process it on the fpga (matched filter). At the end of it all, I have 64 bits that I would like to get off the board every 20ms. Not a big deal right? At such a low data rate, I shouldn't have any questions ..... But I need to offload the data to a pic, (pic18f4550). I know this isn't a pic forum, but for those interested, I was going to use the streaming parallel interface on the PIC for this job. The PIC will then send out the data via 802.11. Now, the stratix is operating at 3.3LVTTL. All my calculations show that I should NOT need level converters to talk to the 5V pic, with the exception of the read/write pin that is asserted by the pic. For that situation, I'll just use a pull up transistor to convert the 5V to 3.3V. Otherwise, my data lines from the FPGA(3.3V) should satisfy the requirements for 5V TTL input operation. Does this sound legit? Thanks Matt