Stratix 2 PLL does not like input clock on/off switching?

Hi,

I've had problems here with a Stratix 2 design that receives an 50 MHz input clock from a remote chip. There are scenarios where this clock is switched off and on again with some 100 ms to seconds of clock "downtime". There is a small amount of logic in the FPGA that reads in a parallel interface which is source synchronous to this clock. This logic ran on a PLL derived copy of this clock. The data is handed to an asynchronous FIFO, so it is really just a small part of the design that operates on this clock.

From time to time there is strange behavior in this input part after such a clock downtime and also in SignalTap instances I connected to the input signals. I also routed the signals to an external logic analyzer interface where the input signals looked quite ok while in the internal logic the input signals seemingly do not appear (state machine does not operate normally, SignalTap does not trigger). The issue occurs about 1 in 50 times.

I reworked the relevant logic to receive a reset which is derived from the PLL locked signal but still the same issues.

Now I attached the input clock signal (which is very well-behaved) directly the input logic, leaving out the PLL, and it worked for ~65k input clock off/on cycles.

I am confused now what might have gone wrong. I do not think it is a simple timing violation on the input since I already transmitted half a terabit over it without a single bit error. The error only happens in connection with clock off/on and interestingly went away nearly always with the next clock off/on cycle but no reset involved.

Best regards,

flintstone