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Altera_Forum
Honored Contributor
Honored ContributorStratix 2 PLL does not like input clock on/off switching?
Hi, I've had problems here with a Stratix 2 design that receives an 50 MHz input clock from a remote chip. There are scenarios where this clock is switched off and on again with some 100 ms to...
Altera_ForumHonored Contributor
Honored ContributorIs it synchronous? E.g. PLL locked signal is not synchronous ant must be synchronized to one of the output clocks.
