Ouups ! You're right Jake.
I've been focusing on the "transceiver" terms and have flown over the "transmitter"...
In that case, an explanation could come from the transmitter local clock divider block.
In fact, each transmitter channel has its own local clock divider that generates the serial and parallel clock for its serializer
when used in non-bonded mode only (is that your case shpavel ?).
If you assume that the parallel clock results from division of the serial clock by a classic counter/divider (DIV4,5,8 or 10) instead of a PLL, one can suppose that at power up, the phase of the divided clock with respect to the serial clock can be any phase amongst the 4,5,8,or 10 possible phase states depending on the counter/divider initial state at power-up
, thus explaining the bit-shift you observe.
Normally, a global tx_digitalreset sequence should prevent such a situation to occur but the accurate scope of the reset is not clearly stated anywhere in the Transceiver Architecture chapter and no circuit implementation details are given about the TX local clock divider.
More over, the GXB TX main application seems to be serialization of independent data streams for high-speed data transmission over backplanes rather than Gbit source synchronous data for a chip-to-chip transmission (but that's another story).
Anyway, I would be interested in knowing the end of your story !
Thanks.
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