Stratix 10 timing result much worse than Arria 10

Question

Hi,
I'm porting design from Arria 10 to Stratix 10, I use Quartus Prime 17.1 for Arria 10, Quartus Prime Pro v2020.2 for Stratix 10. 
I got much worse timing result on Stratix 10 than Arria 10. For example, a clock defined at 13ns period, I got -10ns slack for S10, however it is -1ns for A10. 
I have check the -10ns slack is not due to clock skew, it is single clock domain with no crossing. 
What am I missing when porting design from A10 to S10? Any suggestion is welcomed. 
Thanks.

kennyt_altera · Answer

Due to architecture change for Stratix 10, it will require different method for timing closure in S10. You can refer to the link below for more information:

https://www.intel.com/content/www/us/en/programmable/support/training/course/is10perf.html?wapkw=hyperflex%20timing%20closure

https://www.intel.com/content/www/us/en/programmable/documentation/jbr1444752564689.html?wapkw=hyperflex%20timing%20closure

kennyt_altera · Answer

Since this thread had been answered, we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Forum Discussion

Stratix 10 timing result much worse than Arria 10

2 Replies

Recent Discussions

Asynchronous FIFO and discontinuous write clock

Using Clocklock+Clockboost on EPF10K100GC503-3DX with Quartus 9.0SP2. How?

Arria 10: Remote Update Watchdog unpredicted behavior

Estimate the power consumption of the MAX 10 device 10M08SLV81I7G

[USB-Blaster] Detected as "USB-Blaster Variant" on SLES12 – Causing Detection Issues