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LHinC1's avatar
LHinC1
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5 years ago

Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

Hi Altera AE , We are working on a design on Stratix 10 using PHYLite library. We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any pr...
Rashmi1's avatar
Rashmi1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Just to double confirm, the original design is A10, are you directly migrating this design from A10 to S10 without changing the RTL? The only change you have made is the pin assignments on S10 ?



LHinC1's avatar
LHinC1
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5 years ago

Hello Rashmi,

Thank you for your support.

Our last project was on Arria 10, when we migrate to Stratix 10, I regenerated the PHY Lite library code in Quartus 19.3 / 20.2 (as the library of Arria 10 is not compatible with Stratix 10 device).

And then I connected the PHY Lite in Stratix 10 in the same way as we did on Arria 10.

Regarding "without changing the RTL", for the logic outside the PHY Lite, I think we didn't make any RTL changes.

Thanks,

Samson