Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

Hello Rashmi,

1. 0x05000024 is the base address on the PHY Lite.

2. The issue happened on the very first time when we turn on the FPGA power, and it is never normal after power up nor we do the reset.

3. We have found a way to write a state machine to communicate with the PHY Lite. We do this as a patch, hope this would give you some hints on this issue. I have attached my FSM code here. Please that we added 2 dummy states : SEARCH_INTERFACE_TABLE_0 and SEARCH_INTERFACE_TABLE_VALID_0 to make it work.

Thanks,

Samson