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LHinC1's avatar
LHinC1
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5 years ago

Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

Hi Altera AE , We are working on a design on Stratix 10 using PHYLite library. We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any pr...
Rashmi1's avatar
Rashmi1
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5 years ago

Hi Samson,


  1. How did you get the address, 0x05000024?
  2. Did you reset the board after the issue happens? For example, reset the board and power on, run the design then issue occurs, reset the board and run again.

Thanks,

Rashmi



LHinC1's avatar
LHinC1
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5 years ago

Hello Rashmi,

1. 0x05000024 is the base address on the PHY Lite.

2. The issue happened on the very first time when we turn on the FPGA power, and it is never normal after power up nor we do the reset.

3. We have found a way to write a state machine to communicate with the PHY Lite. We do this as a patch, hope this would give you some hints on this issue. I have attached my FSM code here. Please that we added 2 dummy states : SEARCH_INTERFACE_TABLE_0 and SEARCH_INTERFACE_TABLE_VALID_0 to make it work.

Thanks,

Samson

  • LHinC1's avatar
    LHinC1
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    5 years ago

    Hello Rashmi,

    Excuse me, is there any update?

    Thanks,

    Samson