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LHinC1's avatar
LHinC1
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5 years ago

Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

Hi Altera AE , We are working on a design on Stratix 10 using PHYLite library. We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any pr...
Rashmi1's avatar
Rashmi1
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5 years ago

Hi Samson,


The quartus version 18.1 document is the latest. New version is not yet published yet.


Engineering is still debugging your issue. I havent heard back anything yet.


Thanks,

Rashmi


LHinC1's avatar
LHinC1
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5 years ago

Hi Rashmi,

We are doing simulation on the PHY Lite in ModelSim-Intel on v19.3 and v20.2. We see the data is 0xffffffff when we read a corresponding address on the PHY Lite.

We followed the instructions on AN888, on page 16 - 17, it says: "From the Intel Quartus Prime Pro Edition software, click Processing > Start Compilation to compile the reference design."

And then the next part is Hardware Testing section.

Is there any more information on the steps to perform a post-compilation simulation on the PHY Lite?

Thanks,
Samson

  • LHinC1's avatar
    LHinC1
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    5 years ago

    Hello Rashmi,

    We compiled the design using Quartus Prime v20.2, the result is the same.

    I have attached the picture from Signal Tap and I attached our project archive.

    Thanks,

    Samson