Forum Discussion
Vladimir_Y_Intel
New Contributor
New ContributorStratix 10 performance
Hi, It's been some time we are working with Stratix 10 device. There is a design that we can't close timing on Stratix. After comparing this design on other options (Virtex 7, Ultrascale+), it se...
sstrell
Super Contributor
Super ContributorWithout knowing the design or what you've tried so far, it's hard to tell. If you're not familiar with the Hyperflex architecture (such as the fact that you shouldn't use asynchronous clears), check out online trainings about it, starting here:
https://www.intel.com/content/www/us/en/programmable/support/training/course/os10ihypret.html
