Hello !Working with a Stratix 10 board. Per AN 829: PCI Express* Avalon®-MMDMA Reference Design built the design and uploaded it to the board. I work with Windows. I successfully run DMA Read, DMA Write. After the end of the DMA procedure, I register an MSI interrupt.Than want to additionally register user interrupts. To do this, I use the intx_req_i input, which became available after selecting Export Interrupt conduit interface. And also tried using the rxm_irq_i[15..0] inputs. I apply a logical unit signal of a certain duration to these inputs, but I do not register an interrupt.As I understood from the description, I must first enable interrupts by accessing the PCIe Interrupt Enable Register, which is located at 0x0050.Please tell me how to properly translate the address from BAR in order to access this register from under windows. The map of connections and addresses is shown in the picture. Thank you. .

Hi,Thanks for reaching, Apologize that I cannot get your question very clear.As I understood from the description, I must first enable interrupts by accessing the PCIe Interrupt Enable Register, which is located at 0x0050.Can I know which description and which document that you are referring at ?Please tell me how to properly translate the address from BAR in order to access this register from under windows. Can you specific which BAR that you need to translate ?Also, I attach with AN 829 User guide, it might contain information that needed by you.https://www.intel.com/content/www/us/en/docs/programmable/683554/18-0/working-with-the-reference-design.htmlRegards,Wincent_Intel

Hi, I wish to follow up with you about this forum case.Hoping to hear back from you so that we can proceed for next step. Regards,Wincent_Intel

Hello ! thanks for your reply !Your question : Can I know which description and which document that you are referring at ? This is UG - 20033 (2019.07.18) Intel Stratix10 Avalon - MM Interface for PCI Express Solutions User Guide. 7.2.1. PCI Express Avalon-MM Bridge Register Address Map. Can you specific which BAR that you need to translate ? as shown in the Qsys structure (picture above), from the BAR 0 register I get access to the DMA mechanism. bar4 provides access to the internal memory. at the moment I don’t know how to access the Avalon-MM to PCIe Interrupt Enable Register via CRA thanks for the answer

Hi,For Avalon-MM to PCIe Interrupt Enable Register via CRA,You may refer user guide at below link, there might got the information you needed.https://www.intel.com/content/www/us/en/docs/programmable/683724/18-0/avalon-mm-to-pci-express-interrupt-registers.htmlLet me know if any other further clarification is needed.Regards,Wincent_Intel

Thanks for your reply.I have already seen this documentation many times. But I work with Stratix10 Avalon MM PCIExpress with DMA. I will repeat my question. It is as follows: how do I get access to these registers that you link to. Namely Avalon-MM to PCIe Interrupt Enable Register and Avalon-MM to PCIe Interrupt Status Register. Should it be a call through the BAR or is it a call to the configuration space type 0 , type 1 ?thanks for your reply

Stratix 10 PCI Express Avalon®-MM DMA Reference Design. Interrupt generation.

15 Replies

Volodymir
New Contributor
3 years ago
Hi ! Thanks.

In your last answer you wrote: You need to enable export MSI interface to implement custom MSI interrupt handle and send the MSI interrupt via TXS interface.....

I selected the option in platform designer – Export MSI/MSI-X conduit interface and after then, interface added to the top level of the project:

.intx_req_i (), // input, width = 1, intx_intfc.intx_req

.msi_intfc_o(), // output, width = 82, msi_intfc.msi_intfc

.msi_control_o(), // output, width = 16, msi_control.msi_control

.msix_intfc_o (), // output, width = 16, msix_intfc.msix_intfc

When trigger interrupt using input .intx_req_i (), OS (operating system) register legacy interrupt.

how this interface can help generate MSI interrupt ?

Can you give an example for your recommendations ? about which you wrote:

……….you need to create a MSI (Memory Write) Transaction,

and transmit it through the TXS interface based on the information that you obtain from the MSI conduit interface,

Regards
- Wincent_Altera
  Regular Contributor
  3 years ago
  Hi,
  
  To enable/generate MSI Interrupt. You can refer the link provided in the previous reply.
  
  https://community.intel.com/t5/FPGA-Wiki/Handling-PCIe-Interrupts/ta-p/736044
  
  If you have any doubt, you may refer to the design example , MSI Design Example for Stratix V
  
  It might not exactly the same as Stratix 10. But you can refer to it as a case study.
  
  Hope this is able to help.
  
  Regards,
  
  Wincent_Intel
Wincent_Altera
Regular Contributor
3 years ago
Hi

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__________________________________________________________________________________
Toros
New Contributor
2 years ago
Can this design be run on Stratix 10 AX board?

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Stratix 10 PCI Express Avalon®-MM DMA Reference Design. Interrupt generation.

15 Replies

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