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BeB's avatar
BeB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Stratix 10 Native PHY 10GBASE-R serial loopback: Rx is not always mirroring Tx

Hello, I am using the native PHY configured for 10GBASE-R. I enabled the serial loopback feature to troubleshoot some issues with the Tx path, and found in the process that although the serial loop...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


BeB's avatar
BeB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello,

I spent a bit of time on this issue in the last few weeks, and I can confirm that

- the clocks are definitely stable once coming out of reset

- the same issue arises with 156.25MHz or 644.53125MHz for the reference clock for CDR and ATX PLL (the clocks are provided by a programmable on board oscillator)

So I am back to where I started from: the Rx path does not always mirror the Tx path when the serial loopback is enabled, but all status signals are green.

BeB