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BeB's avatar
BeB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Stratix 10 Native PHY 10GBASE-R serial loopback: Rx is not always mirroring Tx

Hello, I am using the native PHY configured for 10GBASE-R. I enabled the serial loopback feature to troubleshoot some issues with the Tx path, and found in the process that although the serial loop...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Thanks for your clarification that the refclks are coming directly from on-board oscillators. Initially I was confused that they clock might be coming from the Max10 output.


Yes, you are right, it is recommended to use dedicated refclk pin for the TX PLL. In addition to that, you would need to ensure also the clock source is stable and free-running. Just for your information, in some cases, an oscillator is controlled by FPGA which means that FPGA needs to be powered up then only it programs the oscillator. In this case, the clock source is not available during XCVR power up.


Regarding the clock configuration, for CDR, if you select 644.53125MHz refclk frequency, then you need to connect a clock with this 644.53125MHz frequency.


As for the ATX PLL, assuming you are using the same clock source, its configuration should have refclk frequency = 644.53125MHz and output frequency = 5156.25MHz (for 10GBase-R data rate).


Please let me know if there is any concern. Thank you.


BeB's avatar
BeB
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello,

Thank you for the information. I will have to look in more details about clock stability, but if I understand well the design should work equally well with either 156.25MHz or 644.53125MHz for the reference clock for CDR and ATX PLL? And yes, the output frequency of the latter is 5156.25MHz.

Thanks again,

BeB