Occasional Contributor
Regular ContributorHi,
As I understand it, you observe bit error issue when using serial loopback with the 10GBaseR mode Native PHY. This occurs intermittently and depending on the power up. For example, at one power up, it will stay clean. Another power up, it may observe bit error.
For your information, if you are using serial loopback, we could isolate the signal integrity problem from the root cause.
Based on your observation that it is power up dependent, this is trending towards potential calibration related issue. For your information, to ensure a successful power up calibration, you need to provide free-running and stable clock sources to TXPLL and CDR ref clock. These clocks should be directly sourced from on-board oscillator. I notice that the CDR refclk is coming from Max10 device. Can you try with on-board oscillator?
Also, you should feed free-running and stable clock to the OSC_CLK_1 as well.
Please let me know if there is any concern. Thank you.
Occasional ContributorHi,
Thank you for your answer.
I misrepresented the situation: the 156.25MHz is coming from a programmable clock source (Si5341) controlled by a Max10. It is coming in via a differential pair of dedicated clock pins.
I have to say that I am a little confused. I thought that the best clock input option for the Tx PLL was to use a dedicated reference clock pin. Doesn't that imply that the reference clock comes from outside the Stratix 10?
Sorry for the what is probably a basic question, but how should I setup an on-board oscillator for the CDR ref clock?
- The native PHY IP implies that a wide range of frequencies are supported for the CDR ref clock, including 156.25MHz, but what would be the best choice? For example if I pick 10GBASE-R for the native PHY config, the default CDR ref clock is set to 644.53125MHz.
- If I look at the 3 types of PLL for the transceivers:
-- CMU PLL doesn't accept 156.25MHz as an input
-- fPLL accepts 156.25MHz, but what should be the target output frequency? 644.53125MHz?
-- ATX PLL can also accept 156.25MHz and deliver 644.53125MHz for example
Thank you again, and sorry for all the questions. I am having a tough time navigating the documentation.
BeB
