The HyperFlex Architecture is quite a bit different. (Actually, it's very similar except for the Hyper-Register, but it's amazing how many things that impacts and how fundamentally design and timing closure change because of it). I find the three app notes the best for understanding them:
https://www.altera.com/products/fpga/stratix-series/stratix-10/support.html There is other documentation there, and if you go to training there is some shorter free stuff plus some all day training classes you pay for, but are quite good and I recommend to anyone really planning on getting the most performance out of Stratix 10.