Strange problem: design works with SignalTap, but not without it.

Just a quick follow-up, I haven't corrected the problem yet but I do believe it's a timing issue. I don't think we have our Asynchronous RAM configuration set up correctly. The SRAM is a 20ns part, we are running at 50MHz, and we've left the setup / hold / etc. times to 0ns -- where the data sheet indicates they are small but are definitely non-zero. That puts running at 50MHz on the hairy edge.

I'll post another follow-up if correcting that fixes things.

Thanks for the tip on the TimeQuest doc written by rysc! I'll have to check it out. That's one area in FPGA design that is still a bit of "black magic" to me.