Strange problem : Edge capture in a State Machine seems not beeing captured

Hi,

    block_reception : block
    begin
        process_reception : process (clk, reset_n)
            variable detect : std_ulogic_vector(1 downto 0) ; 
            variable cnt : integer range 0 to 5;
        begin
            if reset_n = '0' then
                cnt := 0;
            
                state <= Repos;
                
                ld_rx <= '0';
                sclr_rx <= '0';
                rx_available <= '0';                
                erreur <= '0';                
                pulse <= '0';
               
            elsif rising_edge(clk) then
                detect(1) := detect(0); -- edge capture detection
                detect(0) := clk_iso2;
                -- par défaut
                ld_rx <= '0';
                sclr_rx <= '0';
                rx_available <= '0';
                erreur <= '0';                
                pulse <= '0';
 
                case state is
               
                    -- Repos
                    when Repos=>
                       ...                       
                    
                    when st_wait_ss=>
                        cnt := 0;
                        state <= st_wait_ss;
                        
                        if raz_iso2 = '1' then
                            state <= Repos;
                        elsif code = '1' then 
                            state <= Repos;
                        elsif detect = "10" then -- falling edge
                            ld_rx <= '1';                                
                            ...
                            
                        else
                            state <= st_wait_ss;
                        end if;
                       
                    when st_stock_data=>
                        state <= st_stock_data;
                        if raz_iso2 = '1' then
                          state <= Repos;
                        elsif detect = "10" then -----------------------mistake here, i think----------
                            ld_rx <= '1';
                            
                            cnt := cnt + 1;
                            if cnt > 4 then -- enregistrement tous les 5 fd clk_iso2
                                cnt := 0;
                                ...                                
                            end if;
                            
                        elsif code = '1' then
                            state <= Repos;
                        else
                            state <= st_stock_data;
                        end if;
                    
                    when others => null;
                end case;
            end if;
        end process;
    end block;