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AShiv's avatar
AShiv
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7 years ago

Strange Issue with DE0-Nano-SoC FPGA=>HPS Data Transfer

Hi Everyone, Running into a strange issue with data transfer from the FPGA=>HPS Bridge Data transfer. I am using an Avalon-MM Pipeline Bridge to transfer 32-bit data chunks across the bridge. I have...
AShiv's avatar
AShiv
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7 years ago

I've done the preloader/uboot flash, but I don't think I did anything to configure the bridges from the HPS software, and I wasn't aware that anything needed to be done from that side. I have 1gigabit of DDR3, I malloc'd a section of memory for this task and passed the pointer to the FPGA from the HPS side. I don't think the address was a remap, but I am not positive.

Do you know if I have to create a new device tree ?