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AShiv's avatar
AShiv
Icon for New Contributor rankNew Contributor
7 years ago

Strange Issue with DE0-Nano-SoC FPGA=>HPS Data Transfer

Hi Everyone, Running into a strange issue with data transfer from the FPGA=>HPS Bridge Data transfer. I am using an Avalon-MM Pipeline Bridge to transfer 32-bit data chunks across the bridge. I have...
Daixiwen's avatar
Daixiwen
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I'm not sure what is going on either. I have never used the F2SDRAM bridge before but have several designs with the F2H bridge that work very well.

I assume that you enabled and configured the bridges from the HPS side? You need to be sure you recompiled and reflashed the preloader after you made your modifications in QSys to be sure the bridges are configured correctly, and if I remember correctly they are still not enabled automatically and you need to do it from the HPS software. From my experience trying to use an uninitialised bridge will freeze the Avalon bus but keep the HPS system running.

How much RAM do you have? Did you check that the address that you use is a physical address and not an address remapped elsewhere by the MMU? The bridges won't go through MMU remapping. Those could be stupid questions but I can't think of anything else right now.