Forum Discussion

AShiv's avatar
AShiv
Icon for New Contributor rankNew Contributor
7 years ago

Strange Issue with DE0-Nano-SoC FPGA=>HPS Data Transfer

Hi Everyone, Running into a strange issue with data transfer from the FPGA=>HPS Bridge Data transfer. I am using an Avalon-MM Pipeline Bridge to transfer 32-bit data chunks across the bridge. I have...
AShiv's avatar
AShiv
Icon for New Contributor rankNew Contributor
7 years ago

Hi Daixiwen,

So, I've changed my design a bit so that it now uses the F2SDRAM bridge since I don't need cacheable access. The bridge now goes high at exactly 17 writes every time, but only the first write actually goes to the DDR3, even though the subsequent 16 writes say they go through. In that system I tried changing it so its a multiple of 4 address, but that did not make a difference. I'm not sure what I am doing wrong here...