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AShiv's avatar
AShiv
Icon for New Contributor rankNew Contributor
7 years ago

Strange Issue with DE0-Nano-SoC FPGA=>HPS Data Transfer

Hi Everyone, Running into a strange issue with data transfer from the FPGA=>HPS Bridge Data transfer. I am using an Avalon-MM Pipeline Bridge to transfer 32-bit data chunks across the bridge. I have...
Daixiwen's avatar
Daixiwen
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Could it be that the bridge doesn't like unaligned accesses? Have you tried with addresses multiple of 4? I didn't think it would even work correctly with unaligned accesses. (it doesn't in a Nios2 system at least).