Strange effects with NIOS in design

Thanks for you answer sstrel. I did check the pinout details for my FPGA, but couldn't find anything what could cause my issue. I did also check the compilation report several times, but the only thing I found was the following:

Info (169065): Pin I2C_SCL_NA_MID has a permanently enabled output enable

Info (169065): Pin I2C_SDA_NA_MID has a permanently enabled output enable

I don't think that this is my problem. Still, I think it has to do something with the NIOS. As soon as I remove the NIOS from the design, everything works fine. When looking at the Technology Map Viewer, it shows me that the output pins should be driven to GND (see attached picture).

https://www.alteraforum.com/forum/attachment.php?attachmentid=14189

Also the follwing message in the compilation report tells me that this pins should be driven to GND:

Warning (13032): The following tri-state nodes are fed by constants

Warning (13033): The pin "I2C_AUTH_SCL" is fed by GND

Warning (13033): The pin "I2C_AUTH_SDA" is fed by GND

Warning (13033): The pin "I2C_SCL_NA_MID" is fed by GND

Warning (13033): The pin "I2C_SDA_NA_MID" is fed by GND

So if the compilation report tells me that the pins should be driven by GND and also the Technology Map Viewer shows me a pin which should be driven by GND, it lets me assume that the NIOS has the possibilty to interact directly with the pins and somehow overdrives the pin function. Is this possible? And if so, where could this be configured in the NIOS?