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Altera_Forum
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8 years ago

Strange effects with NIOS in design

Hi everyone, For the first time I am using a NIOS soft core in one of my designs. Generating the core was relatively easy but now I'm facing some strange effects when I integrate the core into ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Ok, let me give you some more details:

I'm using a Cyclone V: 5CGXBC4C7F27C8 and work with Quartus Prime version 17.0 Standard Edition. The Nios consists of the cpu (Nios II/e), the cpu_memory, six PIO output ports and three PIO input ports. The I2C master is located outside the Nios, directly in the design where the Nios should be used. So far I did not connect the Nios to the rest of the design for testing (which means that the Nios is not yet connected to any I2C master so far). There is also no I2C master in the design yet, the two pins which I want to use for I2C communication are driven low by using: I2C_SCL_NA_MID <= '0'; and I2C_SDA_NA_MID <= '0';.

The I2C pins are configured for bidirectional use. The pin assignments are the following:

set_location_assignment PIN_AB22 -to I2C_SCL_NA_MID

set_location_assignment PIN_AC23 -to I2C_SDA_NA_MID

set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to I2C_SCL_NA_MID

set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to I2C_SDA_NA_MID

If I use other pins than PIN_AB22 and PIN_AC23 it works well. And also if I remove the Nios from the design, I'm able to drive these two pins low again. It is only not working if I add the Nios to the design. Is it possible that the Nios takes control of these two pins (or also other pins)?