Strange effect with Stratix FPGA

That doesn't sound right that it's hitting the power supply. I figured if you whole FPGA was toggling at, say >150MHz with truly random data(i.e. 50% toggle rate) you could be using too much power. Once you're in memory, it sounds like a pretty normal design. Are all the IO assigned and correct? (I know that's a loaded question). I'm just guessing something else may be using a lot of power, like IO contention. Not really sure though.