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Altera_Forum
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18 years ago

Strange effect with Stratix FPGA

Hello! I am using a Stratix EP1S10 device on a NIOS II Development Board. I use it for VHDL programming only. That means, I don't use any NIOS stuff in my project. I made my own user configurat...
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Altera_Forum
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18 years ago

Good reply above. Another possibility is that when your shift-register size increases beyond a threshold the synthesis tool could be replacing the logic-element implementation with a RAM block based implementation. To disable this go into "Assignments / Settings / Analysis & Synthesis Settings" then select the "More Settings" box. Set the "Auto Shift Register Replacement" and "Auto Ram Replacement" both to "Off".