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Altera_Forum's avatar
Altera_Forum
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15 years ago

strange behaviour of square root VHDL code

I need a plain VHDL-square root code for a special purpose and used "google code search". I thus found the following code in their files, obviously written by Altera. http://www.google.com/c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Float is not acceptable because I have to be bit true and quick.

I know the Altera MF SqareRoot and used it more than once in projects. In fact I am very happy about this core because it gave my sqr results after only a few clocks fully pipelined also with the slow and small Cyclone devices.

But this time, I need fully portable code in plain VHDL whichs run everywhere and does not use vendor specific MegaFunctions or "CoreGen"s - even if I started with an Altera Implementation

I wouldn't even had asked this in the Altera Forum, if the code did not prentend to come from Altera. Altera might be interested if the code is really wrong, I think. :cool:

So the question is: What is there about the unused signal? Does this show, that the code is incompletely reported ?

It compiles and synthesizes and obviously shows square root behaviour, even if I am not fully sure about the bit slice to use as output at the moment.

What does the tag "restored" in the title mean?

I attached another screenshot with the generic 52 bit output and added the an swapped graph done with image manipulation. This leads to a perfect root.