Forum Discussion
Altera_Forum
Honored Contributor
11 years agostrange behavior of DCFIFO, how to meet the "Functional Timing Requirements"
Hi, My DCFIFO on Cyclone V is broken. Data is lost. depends on FIFO type, MLAB or M10k, data corruption is severer as FIFO larger. I wrote to DCFIFO like this: if(~fifo_fu...
Altera_Forum
Honored Contributor
11 years agoHi Tricky,
I think Sync FIFO has the same behavior. It is not the sync problem. Full is caused by wrreq. So, deassert wrreq after the full setting cycle is the user expected, not the same cycle.