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Altera_Forum
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11 years ago

strange behavior of DCFIFO, how to meet the "Functional Timing Requirements"

Hi, My DCFIFO on Cyclone V is broken. Data is lost. depends on FIFO type, MLAB or M10k, data corruption is severer as FIFO larger. I wrote to DCFIFO like this: if(~fifo_fu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Hi,

My question is how can I deassert wrreq in the SAME cycle?

Can anybody provide some example code?

Thanks!

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use your first code section in a combinatorial way (I assume you have put clock edge statement)