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Honored Contributor
Honored Contributorstrange behavior of DCFIFO, how to meet the "Functional Timing Requirements"
Hi, My DCFIFO on Cyclone V is broken. Data is lost. depends on FIFO type, MLAB or M10k, data corruption is severer as FIFO larger. I wrote to DCFIFO like this: if(~fifo_fu...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi, My question is how can I deassert wrreq in the SAME cycle? Can anybody provide some example code? Thanks! --- Quote End --- use your first code section in a combinatorial way (I assume you have put clock edge statement)
