strang things about FSM

i guess we need more information how you have designed your fsm.

do you have more states than the default ?

how do you change the fsm state ?

is you fsm a meely or a moore state machine ?

could you give us some code snippet ?

I found when irq_i is low,then state machine go to 00000h.see picture nether:

another question:does "if...else if.....else "have priority level?

code:

SPI_IDLE_status:

begin

TXBnCTRL_whetherCanTxNext <= 1'b1;

rxdFIFOHaveFrameIrq <= 1'b1;

SPI_other_CANINTF_irq_reg <= 1'b1;

if(!irq_i)

begin

spiStatusMachineReg <=SPI_CANINTF1;

TXBnCTRL_whetherCanTxNext <= 1'b0;

end

else if(transmitFIFOUsedw>>`wholeFrameLength

begin

TXBnCTRL_whetherCanTxNext <= 1'b0;

txd_FIFO_num_reg <= 15;

spiStatusMachineReg <=SPI_SEND_status;

end

else spiStatusMachineReg <=SPI_IDLE_status;

end

no.

if ( is true )

execute this if 1. if is true

else otherwise if ( this is true )

execute this if 1. if is false and the second is true

else

execure this if none of the if is true

if the first if is true then none of the others are executed

you a.v is not clearly arranged and so hard so read and understand

what i do with fsm is that have one always block that handles only the fsm register and no other register.

spiStatusMachineReg is your fsm register

after reset it seems to start with SPI_config_status

the next state depends upon "addr" but thats an external signal

have you checked the quartus setting about State machine Processing ?

you don#T need to code one hot shot as quartus can change the fsm type if needed.

normaly it is set to one-hot, change it to user encoded so it must keep your coding style. and not modifying it. also signaltap will show you the single states and you can assign names to ist via a table, that makes ist easier to read

Hello

There is one option into quartus that allows you to visualize your Finite State Machines.

Go to

Tools>Netlist viewer>STATE MACHINE VIEWER.

This tool shows very beautifull diagrams of your FSM.

Good Luck.

DABG