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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

storing link rates in ATX PLL

Hi I have gone through the UG :Intel® Arria® 10 DisplayPort IP Core Design Example User Guide UG-20075, In this it uses fpll and stores calibrated link rates for different speeds, can we implem...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Yes, your understanding is correct. ATX PLL need to be recalibrated after a rate change.